VLSI & Digital Circuits: CMOS Inverter, Setup/Hold Time & Static Timing Analysis
Detailed technical questions on CMOS transistor operation, propagation delays, dynamic power dissipation, and flip-flop timing constraints.
In-Depth Interview Questions & Model Solutions
Q1Define Setup Time and Hold Time in sequential flip-flops. What happens during a violation?
Setup Time (Tsetup) is the minimum time data input must remain stable before the active clock edge. Hold Time (Thold) is the minimum time data must remain stable after the active clock edge. A violation leads to Metastability, where the internal output node hovers between logic 0 and logic 1 for an indeterminate time before settling, potentially propagating erratic signals throughout the synchronous pipeline.
- Setup violation occurs when data path is too slow (Max Delay constraint: Tclk >= Tcq + Tcomb + Tsetup).
- Hold violation occurs when data path is too fast (Min Delay constraint: Tcq + Tcomb >= Thold).
- Hold violations cannot be fixed by reducing clock frequency!
Q2Why is the PMOS transistor sized (W/L) roughly 2 to 2.5 times wider than NMOS in a symmetric CMOS inverter?
In Silicon, electron mobility (μn ~ 1350 cm²/V·s) is roughly 2.5 times higher than hole mobility (μp ~ 480 cm²/V·s). For symmetric rise (t_plh) and fall (t_phl) propagation times and a switching threshold at Vdd/2, the transconductance parameters must be equal (βn = βp). Since β = μ * Cox * (W/L), we must compensate for lower hole mobility by making (W/L)_pmos ≈ 2.5 * (W/L)_nmos.
- Electron mobility is 2.5x higher than hole mobility.
- Symmetric sizing equalizes pull-up and pull-down resistances (Rn ≈ Rp).
- Symmetric switching threshold places Vth = Vdd / 2 with equal noise margins (NML = NMH).
Technical Panel Interview Strategy Tips
- Highlight the distinction between dynamic switching power (P = α * C * Vdd² * f) and static subthreshold leakage.